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"write" : "read", REC->reg, REC->len, (u32)(REC->val & 0xffffffff), (u32)(REC->val >> 32)"plane=%d, obj=%p", REC->plane, REC->obj"plane=%d, obj=%p", REC->plane, REC->obj"dev=%u, ring=%u", REC->dev, REC->ring"dev=%u, ring=%u, seqno=%u", REC->dev, REC->ring, REC->seqno"dev=%u, ring=%x, invalidate=%04x, flush=%04x", REC->dev, REC->ring, REC->invalidate, REC->flush"dev=%u, ring=%u, seqno=%u", REC->dev, REC->ring, REC->seqno"dev=%d%s", REC->dev, REC->purgeable ? ", purgeable only" : """dev=%d, size=%d, align=%d %s", REC->dev, REC->size, REC->align, REC->mappable ? ", mappable" : """obj=%p", REC->obj"obj=%p, %s index=%u %s", REC->obj, REC->gtt ? "GTT" : "CPU", REC->index, REC->write ? ", writable" : """obj=%p, offset=%u, len=%u", REC->obj, REC->offset, REC->len"obj=%p, offset=%u, len=%u", REC->obj, REC->offset, REC->len"obj=%p, read=%02x=>%02x, write=%02x=>%02x", REC->obj, REC->read_domains >> 16, REC->read_domains & 0xffff, REC->write_domain >> 16, REC->write_domain & 0xffff"obj=%p, offset=%08x size=%x", REC->obj, REC->offset, REC->size"obj=%p, offset=%08x size=%x%s", REC->obj, REC->offset, REC->size, REC->mappable ? ", mappable" : """obj=%p, size=%u", REC->obj, REC->sizequirk_pipea_forceintel_wait_for_vblankintel_wait_for_pipe_offintel_cancel_fbc_workintel_pin_and_fence_fb_objintel_cpt_verify_modeset@ @sandybridge_update_wm?@@?@ironlake_check_srwmironlake_init_pch_refclkintel_write_eldintel_get_load_detect_pipeintel_release_load_detect_pipeintel_crtc_clock_getintel_increase_pllclockintel_get_pipe_from_crtc_idintel_framebuffer_initironlake_set_drpsironlake_enable_drpsintel_init_emongen6_enable_rpsintel_enable_rc6gen6_update_ring_freqironlake_enable_rc6intel_alloc_context_pagei915_redisable_vgaintel_modeset_initintel_decrease_pllclockintel_init_displayi845_get_fifo_sizei85x_get_fifo_sizei830_get_fifo_size_? i830_update_wmintel_calculate_wmi9xx_get_fifo_size?@_?@? i9xx_update_wmi965_update_wm??@@ @g4x_update_wmg4x_check_srwmg4x_write_eldpineview_update_wm? @@?@ @@?@@ivb_manual_fdi_link_traingen6_fdi_link_trainsandybridge_update_sprite_wmironlake_write_eldironlake_fdi_link_train@@ @ironlake_update_wm?@@?@i8xx_disable_fbci8xx_enable_fbcg4x_disable_fbcg4x_enable_fbcironlake_disable_fbcironlake_enable_fbci9xx_update_planei9xx_get_refclki9xx_crtc_mode_seta0W5O~  *na0W5O  8na0W5O~  pna0W5Ov  pna0W5QZ   a0W5O  Pn  Ng5P@   N\*FxP@  a0W0\`a0W0\`! Ng5p N\*Fx  b N8g5h pUg5h P ag5h  wvg5al  8kg5h *intel_pipe_set_baseintel_update_fbcintel_enable_fbcironlake_update_planeironlake_crtc_mode_setironlake_get_refclkintel_choose_pipe_bpp_ditherironlake_set_pll_edpironlake_crtc_dpmsironlake_pch_enableintel_enable_transcoderintel_disable_pch_portsdisable_pch_dpdisable_pch_hdmiintel_disable_transcoder 6 f  J   C D   >ލH x, \5 : j&V/ 5e M}s ̄ f jmƐ ae n  R 1a  K {5 L|+[  Fv0 :d W s Aq^Q n<l υ ܂  ς֎ ʌintel_get_cxsr_latencyintel_crtc_initintel_crtc_page_flipintel_crtc_cursor_setintel_crtc_dpmsintel_setup_outputsACERZGBDell Inc.XPS 8700intel_crt_initintel_no_crt_dmi_callbackintel_crt_detectintel_crt_detect_hotplugintel_ironlake_crt_detect_hotplugintel_crt_detect_ddcintel_crt_get_edidintel_crt_load_detectAppleMacmini1,1AppleMacmini2,1MSIA9830IMSDell Inc.Studio Hybrid 140gDell Inc.OptiPlex FX170AOpeni965GMx-IF AOpen i915GMx-F AOpen i915GMm-HFS AOpen i45GMx-IAO00001JWClientronU800ClientronE830ASUSTeK Computer INC.EB1007 ASUSTeK Computer INC. AT5NM10T-I Hewlett-Packard t5740 Hewlett-Packardhp t5745 Hewlett-Packardhp st5747 MICRO-STAR INTERNATIONAL CO., LTD MS-7469 Gigabyte Technology Co., Ltd. D525TUDSupermicroX7SPA-HFUJITSUESPRIMO Q900intel_lvds_initintel_no_lvds_dmi_callbackintel_lvds_set_propertyintel_lvds_enableintel_lvds_disableintel_lvds_mode_fixupTOSHIBATECRA A11intel_no_modeset_on_lid_dmi_callbackintel_find_lvds_downclockinit_vbt_defaultsLENOVO97027RGintel_parse_biosparse_general_definitionsparse_sdvo_panel_dataintel_no_opregion_vbt_callbackparse_general_featuresparse_lfp_panel_dataparse_sdvo_device_mappingparse_device_mappingparse_edpintel_dp_initintel_dp_mode_setironlake_edp_pll_onintel_dp_detectintel_dp_sink_dpmsintel_dp_check_edpd Mintel_dp_aux_chintel_dp_start_link_trainintel_gen7_edp_signal_levelsintel_gen6_edp_signal_levelsironlake_edp_panel_onironlake_wait_panel_onironlake_wait_panel_power_cycleironlake_wait_panel_statusintel_dp_complete_link_trainintel_dp_link_downironlake_edp_backlight_onironlake_edp_backlight_offironlake_edp_panel_offironlake_wait_panel_off intel_dp_mode_fixupintel_dp_check_link_statusironlake_panel_vdd_off_syncironlake_edp_panel_vdd_onironlake_edp_panel_vdd_offintel_dp_i2c_initintel_dp_i2c_aux_chintel_hdmi_mode_setintel_infoframe_indexintel_infoframe_flagsintel_sdvo_initintel_sdvo_write_cmdintel_sdvo_debug_write  !'()*+,}zghijklUVWXYZ^_`[\]abcdefMNO{PQRSTmnopqtuvwxyintel_sdvo_write_infoframeintel_sdvo_read_responseintel_sdvo_dpmsintel_sdvo_read_byteintel_sdvo_get_capabilitiesintel_sdvo_output_setupintel_sdvo_detectintel_sdvo_connector_matches_edid320x200@@A320x240@@A400x300@&,-LM640x350@B^_~640x400@J640x480@~X704x480@0` 704x576@0r @A`a720x350@?I0^_~720x400@R0720x480@b0720x540@m0<=720x576@xt0@A`a768x576@R{@`@A`a800x600@ !`XYxy832x624@@Apq920x766@C1024x768@C@` !1280x1024@T@` !intel_sdvo_create_enhance_propertyintel_sdvo_create_enhance_property_tvintel_sdvo_create_enhance_property_lvdsintel_panel_get_max_backlightintel_panel_get_backlightintel_panel_actually_set_backlightintel_panel_setup_backlightinvert_brightnessPPPP P$Pintelfb_createintel_fb_restore_modeintel_tv_init$ @D|YH" @k@Q$ @D|YH" @k 6$ @D|YH" @k@Q$ @D|YH" @k@AP @L_I"  lq\P @L_I   lqC$@JzY ,,P@[_ 00?@E`P,,q @EPP,,  @EPXkO   @E`Xk  n(E2-EYSMNTSC 480i@X Pintel_tv_detect_type XP8 q <2-3-@ 2-3jd z=0@5 . .5@0`5.-4@0`@6.-4 0`6. -3 0`70/,30` 8P/,20`8/ , 20`9/+10` :/`+`1 `:+ 1 @;(*0 @`<8 *0 =8)@0@=H`)0@>H)@`@?X(`` (` (`0@5 . .5@0`5.-4@0`@6.-4 0`6. -3 0`70/,30` 8P/,20`8/ , 20`9/+10` :/`+`1 `:+ 1 @;(*0 @`<8 *0 =8)@0@=H`)0@>H)@`@?X(`` (` (`0@6,-@606-,50@7@-,@507-@,40@8.+@408 .+409@.@+30:`.+@3@0:.*3@0@;.@*2@0<.*@20<.)20@=/@)10= /)10>@/(@10@? /@(@11(/(10@6,-@606-,50@7@-,@507-@,40@8.+@408 .+409@.@+30:`.+@3@0:.*3@0@;.@*2@0<.*@20<.)20@=/@)10= /)10>@/(@10@? /@(@11(/(1q  2-LFZ"2-L"V  q <2-3-@ 2-3jd z= v <2-3-@ 2-3jd z=v2-E?S2-EyO`8`v `8`u@ABintel_ring_setup_status_pageintel_init_ring_bufferinit_status_pageintel_cleanup_ring_bufferinit_ring_commoninit_pipe_controlintel_render_ring_init_drigen6_bsd_ring_write_tailintel_overlay_put_imagei830_activate_pipe_a00 0@0@/00 .0, 0`+ 0 *` 0ീ( 0@? 0x<`@0 : @008@0x6 0@4` 0@2@ 0@`1 000`., h@+@ )`(`>(<9@7 64h`3న@2@1`000intel_overlay_continueintel_overlay_attrsintel_setup_overlayivb_update_planesnb_update_planeintel_opregion_asle_intrintel_opregion_gse_intrintel_opregion_setupch7xxx_readbch7xxx_writebch7xxx_initch7017_dump_regsch7017_mode_setch7017_initivch_readivch_writeivch_inittfp410_readbtfp410_writebtfp410_initsil164_readbsil164_writebsil164_initintel_dsm_pci_probeintel_dsm_detects~ONT,intel_dsmintel_dsm_platform_mux_infoGEM idle failed, resume might fail DRM not initialized, aborting suspend. dev: %p MMIO read or write has been dropped %x /build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/i915_drv.cFound Ibex Peak PCH drmFound CougarPoint PCH Found PatherPoint PCH drm/i915 can't work without intel_agp module! GPU hanging too fast, declaring wedged! Failed to reset chip. i915Intel Graphics20080730called with no initialization tried to set status page when mode setting active /build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/i915_dma.cset status page addr 0x%08x drmcan not ioremap virtual address for G33 hw status page load hws HWS_PGA with gfx mem 0x%x load hws at %p Unknown parameter %d DRM_COPY_TO_USER failed sarea not found assuming DRI2 userspace Client tried to initialize ringbuffer in GEM mode %s can not ioremap virtual address for ring buffer Can not find hardware status page hw status page @ %p Enabled hardware status page <6>i915: switched on <3>i915: switched off unknown parameter %d %s called without lock held, held %d owner %p %p %s: page=%d pfCurrentPage=%d Bad box %d,%d..%d,%d i915 cmdbuffer, buf %p sz %d cliprects %d alignmenti915_dispatch_cmdbuffer failed Batchbuffer ioctl disabled i915 batchbuffer, start %x used %d cliprects %d bridge device not found Failed to initialize GTT inteldrmfbfailed to map registers <6>[drm] MTRR allocation failed. Graphics performance may suffer. i915Failed to create our workqueue. i915 MCHBARfailed bus alloc: %d Can not allocate hardware status page unknown memory frequency 0x%02x unknown fsb frequency 0x%04x <6>[drm] failed to find VBIOS tables FBC base 0x%08lx, ll base 0x%08lx, size %dM not enough stolen space for compressed buffer, disabling hint: you may be able to increase stolen memory size in the BIOS to avoid this failed to init modeset ips_link_to_i915_driverfailed to idle hardware: %d trying to get scanoutpos for disabled pipe %c drmPCH audio power change on port %d PCH GMBUS interrupt PCH HDCP audio interrupt PCH transcoder audio interrupt PCH poison interrupt pipe %c FDI IIR: 0x%08x PCH transcoder CRC done interrupt PCH transcoder CRC error interrupt PCH transcoder B underrun interrupt PCH transcoder A underrun interrupt Kicking stuck wait on %s ERROR=1RESET=1ERROR=0resetting chip running encoder hotplug functions trying to get vblank count for disabled pipe %c Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ? Invalid crtc %d crtc %d is disabled out of memory, not capturing error state <6>[drm] capturing error event; look for more information in /debug/dri/%d/i915_error_state <3>render error detected, EIR: 0x%08x <3> IPEIR: 0x%08x <3> IPEHR: 0x%08x <3> INSTDONE: 0x%08x <3> INSTPS: 0x%08x <3> INSTDONE1: 0x%08x <3> ACTHD: 0x%08x <3>page table error <3> PGTBL_ER: 0x%08x <3>memory refresh error: <3>pipe %c stat: 0x%08x <3>instruction error <3> INSTPM: 0x%08x EIR stuck: 0x%08x, masking pipe %c underrun hotplug event received, stat 0x%08x Pageflip stall detected called with no initialization %s called without lock held, held %d owner %p %p copy_to_user irq_nr=%d breadcrumb=%d EBUSY -- rec: %d emitted: %d Hangcheck timer elapsed... GPU hung Manually setting uncore sharing to %d drm%d max freq: %d wedged : %d Manually setting max freq to %d <6>[drm] Manually setting wedged to %d GFX_MODE: 0x%08x %s PP_DIR_BASE: 0x%08x PP_DIR_BASE_READ: 0x%08x PP_DIR_DCLV: 0x%08x aliasing PPGTT: pd gtt offset: 0x%08x ECOCHK: 0x%08x purgeable dirty Pp%pK: %s%s %8zdKiB %04x %04x %d %d%s%s%s (name: %d) (fence: %d) (gtt offset: %08x, size: %08x) (%s mappable) (%s)power context render context fbcon size: %d x %d, depth %d, %d bpp, obj user size: %d x %d, depth %d, %d bpp, obj enableddisabledself-refresh: %s GFXEC: %ld INTTOEXT%02d: 0x%08x P%02dVIDFREQ: 0x%08x (VID: %d) %s command stream: HEAD: 0x%08x TAIL: 0x%08x ACTHD: 0x%08x IPEIR: 0x%08x IPEHR: 0x%08x INSTDONE: 0x%08x INSTDONE1: 0x%08x BBADDR: 0x%08llx INSTPS: 0x%08x INSTPM: 0x%08x FADDR: 0x%08x FAULT_REG: 0x%08x SYNC_0: 0x%08x SYNC_1: 0x%08x seqno: 0x%08x ring->head: 0x%08x ring->tail: 0x%08x P p%s [%d]: %08x %8u %04x %04x %08x%s%s%s%s%s%s%sNo ringbuffer setup %08x : %08x 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x Current sequence (%s): %d Waiter sequence (%s): %d IRQ sequence (%s): %d Interrupt enable: %08x Interrupt identity: %08x Interrupt mask: %08x Pipe %c stat: %08x North Display Interrupt enable: %08x North Display Interrupt identity: %08x North Display Interrupt mask: %08x South Display Interrupt enable: %08x South Display Interrupt identity: %08x South Display Interrupt mask: %08x Graphics Interrupt enable: %08x Graphics Interrupt identity: %08x Graphics Interrupt mask: %08x Interrupts received: %d Graphics Interrupt mask (%s): %08x Reserved fences = %d Total fences = %d Fenced object[%2d] = unusedRender requests: %d @ %d BSD requests: BLT requests: No requests Active: Inactive: Pinned: Flushing: Deferred free: Total %d objects, %zu bytes, %zu GTT size %u objects, %zu bytes %u [%u] objects, %zu [%zu] bytes in gtt %u [%u] active objects, %zu [%zu] bytes %u [%u] pinned objects, %zu [%zu] bytes %u [%u] inactive objects, %zu [%zu] bytes %u [%u] freed objects, %zu [%zu] bytes %u pinned mappable objects, %zu bytes %u fault mappable objects, %zu bytes %zu [%zu] gtt total yesnogen: %d pch: %d is_mobile: %s is_i85x: %s is_i915g: %s is_i945gm: %s is_g33: %s need_gfx_hws: %s is_g4x: %s is_pineview: %s is_broadwater: %s is_crestline: %s has_fbc: %s has_pipe_cxsr: %s has_hotplug: %s cursor_needs_physical: %s has_overlay: %s overlay_needs_physical: %s supports_tv: %s has_bsd_ring: %s has_blt_ring: %s has_llc: %s bugbit6 swizzle for X-tiling = %s bit6 swizzle for Y-tiling = %s DDC = 0x%08x C0DRB3 = 0x%04x C1DRB3 = 0x%04x MAD_DIMM_C0 = 0x%08x MAD_DIMM_C1 = 0x%08x MAD_DIMM_C2 = 0x%08x TILECTL = 0x%08x ARB_MODE = 0x%08x DISP_ARB_CTL = 0x%08x w/ctx: %d, w/o ctx: %d forcewake count = %u FBC unsupported on this chipset FBC enabled FBC disabled: no outputsnot enough stolen memorymode not supportedmode too largeFBC unsupported on planescanout buffer not tiledmultiple pipes are enableddisabled per module param (default off)unknown reasonunsupported on this chipset GPU freq (MHz) Effective CPU freq (MHz) pcode read of freq table timed out %d %d GMCH temp: %ld Chipset power: %ld GFX power: %ld Total power: %ld RC information inaccurate because somebody holds a forcewake reference RC information accurate: %s Video Turbo Mode: %s HW control enabled: %s SW control enabled: %s RC1e Enabled: %s RC6 Enabled: %s Deep RC6 Enabled: %s Deepest RC6 Enabled: %s Current RC state: Core Power Down on RC3 RC6 RC7 Unknown Core Power Down: %s HD boost: %s Boost freq: %d Gated voltage change: %s Starting frequency: P%d Max P-state: P%d Min P-state: P%d RS1 VID: %d RS2 VID: %d Render standby enabled: %s Current RS state: RC1 RC1E RS1 RS2 (RC6) RC3 (RC6+) unknown Requested P-state: %d Requested VID: %d Current VID: %d Current P-state: %d GT_PERF_STATUS: 0x%08x RPSTAT1: 0x%08x Render p-state ratio: %d Render p-state VID: %d Render p-state limit: %d CAGF: %dMHz RP CUR UP EI: %dus RP CUR UP: %dus RP PREV UP: %dus RP CUR DOWN EI: %dus RP CUR DOWN: %dus RP PREV DOWN: %dus Lowest (RPN) frequency: %dMHz Nominal (RP1) frequency: %dMHz Max non-overclocked (RP0) frequency: %dMHz no P-state info available no error state collected Time: %ld s %ld us Kernel: 3.2.0-4-amd64 PCI ID: 0x%04x EIR: 0x%08x PGTBL_ER: 0x%08x fence[%d] = %08llx ERROR: 0x%08x DONE_REG: 0x%08x ActivePinned%s --- gtt_offset = 0x%08x %s --- %d requests seqno 0x%08x, emitted %ld, tail 0x%08x %s --- ringbuffer = 0x%08x No flip due on pipe %c (plane %c) Flip queued on pipe %c (plane %c) Flip pending (waiting for vsync) on pipe %c (plane %c) Stall check enabled, Stall check waiting for page flip ioctl, %d prepares Old framebuffer gtt_offset 0x%08x New framebuffer gtt_offset 0x%08x Ring %s: Head : %08x Tail : %08x Size : %08x Active : %08x NOPID : %08x Sync 0 : %08x Sync 1 : %08x Control : %08x Start : %08x i915_wedgedi915_forcewake_useri915_max_freqi915_cache_sharingi915_capabilitiesi915_gem_objectsi915_gem_gtti915_gem_activei915_gem_flushingi915_gem_inactivei915_gem_pinnedi915_gem_deferred_freei915_gem_pageflipi915_gem_requesti915_gem_seqnoi915_gem_fence_regsi915_gem_interrupti915_gem_hwsi915_gem_hws_blti915_gem_hws_bsdi915_ringbuffer_datai915_ringbuffer_infoi915_bsd_ringbuffer_datai915_bsd_ringbuffer_infoi915_blt_ringbuffer_datai915_blt_ringbuffer_infoi915_error_statei915_rstdby_delaysi915_cur_delayinfoi915_delayfreq_tablei915_inttoext_tablei915_drpc_infoi915_emon_statusi915_ring_freq_tablei915_gfxeci915_fbc_statusi915_sr_statusi915_opregioni915_gem_framebufferi915_context_statusi915_gen6_forcewake_counti915_swizzle_infoi915_ppgtt_infononebit9bit9/bit10bit9/bit11bit9/bit10/bit11unkownbit9/bit17bit9/bit10/bit17 uncached snooped (LLC) snooped (LLC+MLC)XYrenderbsdblt X Y/build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/i915_gem.cAttempting to bind a purgeable object Invalid object alignment requested %u Attempting to bind an object larger than the aperture Attempting to mmap a purgeable buffer something (likely vbetool) disabled interrupts, re-enabling object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned object 0x%08x not 512K or pot-size 0x%08x aligned can not change the cache level of pinned objects drmAttempting to unbind pinned buffer bo is already pinned with incorrect alignment: offset=%x, req.alignment=%x, req.map_and_fenceable=%d, obj->map_and_fenceable=%d Attempting to pin a purgeable buffer Already pinned in i915_gem_pin_ioctl(): %d Not pinned by caller in i915_gem_pin_ioctl(): %d Reenabling wedged hardware, good luck failed to idle hardware: %d failed to init phys object %d size: %zu /build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/i915_gem_evict.cNo GTT space found for object %d drmreloc with multiple write domains: obj %p target %d offset %d read %08x write %08xreloc with read/write non-GPU domains: obj %p target %d offset %d read %08x write %08xWrite domain conflict: obj %p target %d offset %d new %08x old %08x Relocation beyond object bounds: obj %p target %d offset %d size %d. Relocation not 4-byte aligned: obj %p target %d offset %d. /build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/i915_gem_execbuffer.cexecbuf with invalid offset/length execbuf with invalid ring (BSD) execbuf with invalid ring (BLT) execbuf with unknown ring: %d execbuf with unknown constants: %d execbuf with %d buffers clip rectangles are only valid with the render ring execbuf with %u cliprects Invalid object handle %d at index %d Object %p [handle %d, index %d] appears more than once in object list Attempting to use self-modifying batch buffer Failed to allocate exec list for %d buffers copy %d exec entries failed %d failed to copy %d exec entries back to user (%d) execbuf2 with %d buffers /build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/i915_gem_gtt.cCouldn't idle GPU Couldn't read from MCHBAR. Disabling tiling. unknown tiling mode Failed to allocate memory for bit 17 record writeread/build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/./i915_trace.h%s: %s reg=0x%x, len=%d, val=(0x%x, 0x%x) plane=%d, obj=%p dev=%u, ring=%u dev=%u, ring=%u, seqno=%u dev=%u, ring=%x, invalidate=%04x, flush=%04x , purgeable onlydev=%d%s , mappabledev=%d, size=%d, align=%d %s obj=%p , writableGTTCPUobj=%p, %s index=%u %s obj=%p, offset=%u, len=%u obj=%p, read=%02x=>%02x, write=%02x=>%02x obj=%p, offset=%08x size=%x obj=%p, offset=%08x size=%x%s obj=%p, size=%u objstruct drm_i915_gem_object *valu64regu32u16lenplaneintdevringseqnoinvalidateflushpurgeableboolsizealignmappableindexgttoffsetread_domainswrite_domaini915_reg_rwi915i915_flip_completei915_flip_requesti915_ring_wait_endi915_ring_wait_begini915_gem_request_wait_endi915_gem_request_wait_begini915_gem_request_retirei915_gem_request_completei915_gem_request_addi915_gem_ring_flushi915_gem_ring_dispatchi915_gem_evict_everythingi915_gem_evicti915_gem_object_destroyi915_gem_object_clflushi915_gem_object_faulti915_gem_object_preadi915_gem_object_pwritei915_gem_object_change_domaini915_gem_object_unbindi915_gem_object_bindi915_gem_object_create<6>[drm] applying no-PCH_PWM_ENABLE quirk <6>[drm] Backlight polarity reversed on %s applying pipe a force quirk drmUnknown FSB/MEM found, disable CxSR FIFO entries required for mode: %ld FIFO watermark level: %ld BAFIFO size - (0x%08x) %s: %d Setting FIFO watermarks - A: %d FIFO watermarks - A: %d, B: %d self-refresh entries: %d Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d memory self refresh enabled memory self refresh disabled self-refresh entries: %d, wm: %d self-refresh watermark: display plane %d cursor %d Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d ELD size %d DSPFW1 register is %x DSPFW3 register is %x Self-refresh is enabled Self-refresh is disabled enabled FBC, pitch %d, yoff %d, plane %d, disabled FBC enabled fbc on plane %d Disabling pch HDMI %x on pipe %d panel assertion failure, pipe %c regs locked /build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/intel_display.conoffplane %c assertion failure (expected %s, current %s) FDI TX state assertion failure (expected %s, current %s) FDI RX state assertion failure (expected %s, current %s) FDI_RX_IIR 0x%x FDI train 1 done. FDI train 2 done. FDI train done. FDI train 1 fail! FDI train 2 fail! Can't update plane %d in SAREA Unknown color depth %d Writing base %08lX %08lX %d %d %d Can't update pipe %c in SAREA failed to alloc power context, RC6 disabled failed to pin power context: %d failed to set-domain on power context: %d FBC idle timed out Sandybridge: deep RC6 disabled RC6 and deep RC6 enabled Disabling pch dp %x on pipe %d watermark %d: display plane %d, fbc lines %d, cursor %d fbc watermark(%d) is too large(%d), disabling wm%d+ display watermark(%d) is too large(%d), disabling wm%d+ cursor watermark(%d) is too large(%d), disabling wm%d+ latency %d is 0, disabling wm%d+ FIFO watermarks For pipe A - plane %d, cursor: %d FIFO watermarks For pipe B - plane %d, cursor: %d FIFO watermarks For pipe C - plane %d, cursor: %d PCH DP (0x%08x) enabled on transcoder %c, should be disabled PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled cancelling pending FBC enable SR watermark: display plane %d, cursor %d display watermark is too large(%d/%ld), disabling cursor watermark is too large(%d/%ld), disabling SR latency is 0, disabling Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d failed to compute sprite wm for pipe %d sprite watermarks For pipe %d - %d failed to compute sprite lp1 wm on pipe %d failed to compute sprite lp2 wm on pipe %d failed to compute sprite lp3 wm on pipe %d ELD on pipe %c Audio directed to unknown port ELD on port %c ELD: DisplayPort detected vblank wait timed out upclocking LVDS failed to upclock LVDS! PLL state assertion failure (expected %s, current %s) FDI RX PLL assertion failure, should be active but is disabled FDI TX PLL assertion failure, should be active but is disabled downclocking LVDS failed to downclock LVDS! pipe_off wait timed out plane %c assertion failure, should be off on pipe %c but is still active plane %c assertion failure, should be disabled but not pipe %c assertion failure (expected %s, current %s) FDI train done more than one pipe active, disabling compression no output, disabling fbc set to per-chip default fbc disabled per module param framebuffer too large, disabling compression mode incompatible with compression, disabling mode too large for compression, disabling plane not 0, disabling compression framebuffer not tiled or fenced, disabling compression disabling active FBC for update scheduling delayed FBC enable unsupported config, disabling FBC flip queue: crtc already busy Y tiled not allowed for scan out buffers unknown plane in flip command No FB bound no plane for crtc pin & fence failed failed to update base address mode set failed: pipe %d stuck has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d Using SSC on panel Using SSC on eDP Disabling SSC entirely ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s] [CONNECTOR:%d:%s], [ENCODER:%d:%s] Unknown DPLL mode %08x in programmed mode using SSC reference clock of %d MHz Couldn't find PLL settings for mode! Mode for pipe %c: <6>[drm] Changing LVDS panel from (%chsync, %cvsync) to (%chsync, %cvsync) enabling CxSR downclocking disabling CxSR downclocking clamping display bpc (was %d) to LVDS (%d) clamping display bpc (was %d) to EDID reported max of %d clamping display bpc (was %d) to eDP (%d) forcing bpc to 12 for HDMI forcing bpc to 8 for HDMI Dithering DP to 6bpc unsupported depth, assuming 24 bits setting pipe bpc to %d (max display bpc %d) intel_choose_pipe_bpp returned invalid value %d Mode for pipe %d: using pipe a dpll using pipe b dpll no matching PLL configuration for pipe 2 eDP PLL enable for clock %d PCH refclk assertion failure, should be active but is disabled Wrong PCH DP port return. Guess port B transcoder %d PLL not enabled PCH PLL state assertion failure (expected %s, current %s) failed to enable transcoder %d failed to disable transcoder %d transcoder assertion failed, should be off on pipe %c but is still active disable lvds on pipe %d val 0x%08x PCH VGA enabled on transcoder %c, should be disabled PCH LVDS enabled on transcoder %c, should be disabled crtc %d/%d dpms on crtc %d/%d dpms off cursor off we currently only support 64x64 cursors buffer is to small cursor cannot be tiled failed to move cursor bo into the GTT failed to release fence for cursorfailed to attach phys object called with no initialization no such CRTC id unsupported pixel format %u framebuffer init failed %d no pipe available for load-detect creating tmp fb for load-detection reusing fbdev for load-detection framebuffer failed to allocate framebuffer for load-detection failed to set mode on load-detect pipe gpu busy, RCS change rejected fmax: %d, fmin: %d, fstart: %d stuck trying to change perf mode bad pxval: %ld GT fifo had a previous error %x <6>[drm] Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s timeout waiting for pcode mailbox to become idle timeout waiting for pcode mailbox to finish overclocking supported, adjusting frequency max to %dMHz pcode write of freq table timed out failed to enable ironlake power power savings Something enabled VGA plane, disabling it 32sUsing MT version of forcewake Failed to get proper latency. Disable CxSR Failed to read display plane latency. Disable CxSR <6>[drm] failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR %d display pipe%s available. swapping pipes & planes for FBC plane %d init failed: %d probing SDVOB probing HDMI on SDVOB probing DP_B probing SDVOC probing HDMI on SDVOC probing DP_C probing DP_D Pipe [%d]: CONF: %08x SRC: %08x HTOTAL: %08x HBLANK: %08x HSYNC: %08x VTOTAL: %08x VBLANK: %08x VSYNC: %08x Plane [%d]: CNTR: %08x STRIDE: %08x SIZE: %08x POS: %08x ADDR: %08x SURF: %08x TILEOFF: %08x Cursor [%d]: BASE: %08x NCR CorporationSkipping CRT initialization for %s drmCRT GMBUS EDID read failed, retry using GPIO bit-banging CRT detected via DDC:0x50 [EDID] CRT not detected via DDC:0x50 [EDID reports a digital panel] trigger hotplug detect cycle: adpa=0x%x timed out waiting for FORCE_TRIGGERironlake hotplug adpa=0x%x, result %d timed out waiting for FORCE_DETECT to go offCRT detected via hotplug CRT not detected via hotplug starting load-detect on CRT pch crt adpa set to 0x%x ACER ZGBDELL XPS 8700Skipping LVDS initialization for %s drmSkipping forced modeset for %s Can't support LVDS on pipe A Can't enable LVDS and another encoder on the same pipe applying panel-fitter: %x, %x timed out waiting for panel to power on timed out waiting for panel to power off no scaling not supported disable LVDS for eDP support LVDS downclock is found in EDID. Normal clock %dKhz, downclock %dKhz lid notifier registration failed No LVDS modes found, disabling. LVDS is not present in VBT Apple Mac Mini (Core series)Apple Mac Mini (Core 2 series)MSI IM-945GSE-ADell Studio HybridDell OptiPlex FX170AOpen Mini PCAOpen Mini PC MP915AOpen i915GMm-HFSAOpen i45GMx-IAopen i945GTt-VFAClientron U800Clientron E830Asus EeeBox PC EB1007Asus AT5NM10T-IHewlett-Packard HP t5740Hewlett-Packard t5745Hewlett-Packard st5747MSI Wind Box DC500Gigabyte GA-D525TUDSupermicro X7SPA-HFujitsu Esprimo Q900Toshiba Tecra A11Falling back to manually reading VBT from VBIOS ROM for %s drmSDVOBSDVOCSet default to SSC at %dMHz $VBTUsing VBT from OpRegion: %20s VBT signature missing BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d crt_ddc_bus_pin: %d BDB_GD too small (%d). Invalid. Found panel mode in BIOS VBT tables: LVDS downclock is found in VBT. Normal Clock %dKHz, downclock %dKHz VBT initial LVDS value %x Found SDVO panel mode in BIOS VBT tables: No general definition block is found, unable to construct sdvo mapping. different child size is found. Invalid. Incorrect SDVO port. Skip it the SDVO device with slave addr %2x is found on %s port SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d Maybe one SDVO port is shared by two SDVO device. there exists the slave2_addr. Maybe this is a SDVO device with multiple inputs. No SDVO device info is found in VBT No general definition block is found, no devices defined. no child dev is parsed from VBT No memory space for child device No eDP BDB found but eDP panel supported. ThinkCentre A57Unsupported voltage swing/pre-emphasis level:0x%x drm Display port link bw %02x lane count %d clock %d PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x eDP powered off while attempting aux channel communication. /build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/intel_dp.cStatus 0x%08x Control 0x%08x dp_aux_ch not done status 0x%08x dp_aux_ch receive error status 0x%08x dp_aux_ch timeout status 0x%08x dp_aux_ch not started status 0x%08x training pattern 1 signal levels %08x failed to get link status clock recovery OK too many full retries, give up too many voltage retries, give up failed to train DP, aborting CP or sink specific irq unhandled %s: channel EQ not ok, retraining aux_ch failed %d aux_ch native nack aux_ch invalid native reply 0x%02x aux_i2c nack aux_i2c defer aux_i2c invalid reply 0x%02x too many retries, giving up Enabling DP audio on pipe %c failed to write sink power state mask %08x value %08x status %08x control %08x Panel status timeout: status %08x control %08x Wait for panel power cycle Turn eDP VDD on eDP VDD already requested on eDP VDD already on eDP was not running Turn eDP power on eDP power already on Wait for panel power on Turn eDP power off Need VDD to turn off panel Wait for panel power off time Turn eDP VDD off %d eDP VDD not forced onDPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx DPDDC-ADPDDC-BDPDDC-CDPDDC-Dcur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d panel power up delay %d, power down delay %d, power cycle delay %d backlight on delay %d, off delay %d <6>[drm] failed to retrieve link info, disabling eDP i2c_init %s unknown info frame type %d drmEnabling HDMI audio on pipe %c IntelIntegrated gfxi2c transfer returned %d drmSDVOBSDVOC%s: R: (%s)(??? %d) %02X ... failed %s: W: %02X %02X I2c transfer returned %d I2c transfer returned %d/%d (%02X)First %s output reported failure to sync connector_is_digital? %d, monitor_is_digital? %d No enhancement is supported left_marginright_marginh_overscan: max %d, default %d, current %d top_marginbottom_marginv_overscan: max %d, default %d, current %d hposhpos: max %d, default %d, current %d vposvpos: max %d, default %d, current %d saturationsaturation: max %d, default %d, current %d contrastcontrast: max %d, default %d, current %d huehue: max %d, default %d, current %d sharpnesssharpness: max %d, default %d, current %d brightnessbrightness: max %d, default %d, current %d flicker_filterflicker_filter: max %d, default %d, current %d flicker_filter_adaptiveflicker_filter_adaptive: max %d, default %d, current %d flicker_filter_2dflicker_filter_2d: max %d, default %d, current %d tv_chroma_filtertv_chroma_filter: max %d, default %d, current %d tv_luma_filtertv_luma_filter: max %d, default %d, current %d dot_crawldot crawl: current %d writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i modeSDVO response %d %d [%x] SDVO DDC proxyNo SDVO device found on SDVO%c SDVO capabilities: vendor_id: %d device_id: %d device_rev_id: %d sdvo_version_major: %d sdvo_version_minor: %d sdvo_inputs_mask: %d smooth_scaling: %d sharp_scaling: %d up_scaling: %d down_scaling: %d stall_support: %d output_flags: %d %s: Unknown SDVO output type (0x%02x%02x) SDVO output failed to setup on SDVO%c %s device VID/DID: %02X:%02X.%02X, clock range %dMHz - %dMHz, input 1: %c, input 2: %c, output 1: %c, output 2: %c SDVO_CMD_RESETSDVO_CMD_GET_DEVICE_CAPSSDVO_CMD_GET_FIRMWARE_REVSDVO_CMD_GET_TRAINED_INPUTSSDVO_CMD_GET_ACTIVE_OUTPUTSSDVO_CMD_SET_ACTIVE_OUTPUTSSDVO_CMD_GET_IN_OUT_MAPSDVO_CMD_SET_IN_OUT_MAPSDVO_CMD_GET_ATTACHED_DISPLAYSSDVO_CMD_GET_HOT_PLUG_SUPPORTSDVO_CMD_SET_ACTIVE_HOT_PLUGSDVO_CMD_GET_ACTIVE_HOT_PLUGSDVO_CMD_GET_INTERRUPT_EVENT_SOURCESDVO_CMD_SET_TARGET_INPUTSDVO_CMD_SET_TARGET_OUTPUTSDVO_CMD_GET_INPUT_TIMINGS_PART1SDVO_CMD_GET_INPUT_TIMINGS_PART2SDVO_CMD_SET_INPUT_TIMINGS_PART1SDVO_CMD_SET_INPUT_TIMINGS_PART2SDVO_CMD_SET_OUTPUT_TIMINGS_PART1SDVO_CMD_SET_OUTPUT_TIMINGS_PART2SDVO_CMD_GET_OUTPUT_TIMINGS_PART1SDVO_CMD_GET_OUTPUT_TIMINGS_PART2SDVO_CMD_CREATE_PREFERRED_INPUT_TIMINGSDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGESDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGESDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTSSDVO_CMD_GET_CLOCK_RATE_MULTSDVO_CMD_SET_CLOCK_RATE_MULTSDVO_CMD_GET_SUPPORTED_TV_FORMATSSDVO_CMD_GET_TV_FORMATSDVO_CMD_SET_TV_FORMATSDVO_CMD_GET_SUPPORTED_POWER_STATESSDVO_CMD_GET_POWER_STATESDVO_CMD_SET_ENCODER_POWER_STATESDVO_CMD_SET_DISPLAY_POWER_STATESDVO_CMD_SET_CONTROL_BUS_SWITCHSDVO_CMD_GET_SDTV_RESOLUTION_SUPPORTSDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORTSDVO_CMD_GET_SUPPORTED_ENHANCEMENTSSDVO_CMD_GET_MAX_HPOSSDVO_CMD_GET_HPOSSDVO_CMD_SET_HPOSSDVO_CMD_GET_MAX_VPOSSDVO_CMD_GET_VPOSSDVO_CMD_SET_VPOSSDVO_CMD_GET_MAX_SATURATIONSDVO_CMD_GET_SATURATIONSDVO_CMD_SET_SATURATIONSDVO_CMD_GET_MAX_HUESDVO_CMD_GET_HUESDVO_CMD_SET_HUESDVO_CMD_GET_MAX_CONTRASTSDVO_CMD_GET_CONTRASTSDVO_CMD_SET_CONTRASTSDVO_CMD_GET_MAX_BRIGHTNESSSDVO_CMD_GET_BRIGHTNESSSDVO_CMD_SET_BRIGHTNESSSDVO_CMD_GET_MAX_OVERSCAN_HSDVO_CMD_GET_OVERSCAN_HSDVO_CMD_SET_OVERSCAN_HSDVO_CMD_GET_MAX_OVERSCAN_VSDVO_CMD_GET_OVERSCAN_VSDVO_CMD_SET_OVERSCAN_VSDVO_CMD_GET_MAX_FLICKER_FILTERSDVO_CMD_GET_FLICKER_FILTERSDVO_CMD_SET_FLICKER_FILTERSDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVESDVO_CMD_GET_FLICKER_FILTER_ADAPTIVESDVO_CMD_SET_FLICKER_FILTER_ADAPTIVESDVO_CMD_GET_MAX_FLICKER_FILTER_2DSDVO_CMD_GET_FLICKER_FILTER_2DSDVO_CMD_SET_FLICKER_FILTER_2DSDVO_CMD_GET_MAX_SHARPNESSSDVO_CMD_GET_SHARPNESSSDVO_CMD_SET_SHARPNESSSDVO_CMD_GET_DOT_CRAWLSDVO_CMD_SET_DOT_CRAWLSDVO_CMD_GET_MAX_TV_CHROMA_FILTERSDVO_CMD_GET_TV_CHROMA_FILTERSDVO_CMD_SET_TV_CHROMA_FILTERSDVO_CMD_GET_MAX_TV_LUMA_FILTERSDVO_CMD_GET_TV_LUMA_FILTERSDVO_CMD_SET_TV_LUMA_FILTERSDVO_CMD_GET_SUPP_ENCODESDVO_CMD_GET_ENCODESDVO_CMD_SET_ENCODESDVO_CMD_SET_PIXEL_REPLISDVO_CMD_GET_PIXEL_REPLISDVO_CMD_GET_COLORIMETRY_CAPSDVO_CMD_SET_COLORIMETRYSDVO_CMD_GET_COLORIMETRYSDVO_CMD_GET_AUDIO_ENCRYPT_PREFERSDVO_CMD_SET_AUDIO_STATSDVO_CMD_GET_AUDIO_STATSDVO_CMD_GET_HBUF_INDEXSDVO_CMD_SET_HBUF_INDEXSDVO_CMD_GET_HBUF_INFOSDVO_CMD_GET_HBUF_AV_SPLITSDVO_CMD_SET_HBUF_AV_SPLITSDVO_CMD_GET_HBUF_TXRATESDVO_CMD_SET_HBUF_TXRATESDVO_CMD_SET_HBUF_DATASDVO_CMD_GET_HBUF_DATAPower onSuccessNot supportedInvalid argPendingTarget not specifiedScaling not supportedNTSC_MNTSC_JNTSC_443PAL_BPAL_DPAL_GPAL_HPAL_IPAL_MPAL_NPAL_NCPAL_60SECAM_BSECAM_DSECAM_GSECAM_KSECAM_K1SECAM_LSECAM_60audioBroadcast RGBforce-dvioffautoonFullLimited 16:235<4>fixme: max PWM is zero. max backlight PWM = %d drmset backlight PWM = %d get backlight PWM = %d /build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/intel_panel.cintel_backlightFailed to register backlight: %ld <6>[drm] GMBUS timed out waiting for idle <6>[drm] GMBUS timed out, falling back to bit banging on pin %d [%s] &dev_priv->gmbus_mutexi915 gmbus %sdisabledsscvgapaneldpcdpbreserveddpdfailed to allocate framebuffer failed to pin fb: %d inteldrmfballocated %dx%d fb: 0x%08x, bo %p drmfailed to restore crtc mode TV detected: %x, %x drmDetected Composite TV connection Detected S-Video TV connection Detected Component TV connection Unrecognised TV connection NTSC-MIntegrated TV is not present. NTSC-443NTSC-JPAL-MPAL-NPAL480p576p720p@60Hz720p@50Hz1080i@50Hz1080i@60Hz640x480800x6001024x7681280x1024848x4801280x7201920x1080sil164ch7xxxivchtfp410ch7017timed out waiting for IDLE Indicator %s head not reset to zero ctl %08x head %08x tail %08x start %08x drmfailed to set %s head to zero ctl %08x head %08x tail %08x start %08x %s initialization failed ctl %08x head %08x tail %08x start %08x Failed to allocate seqno page %s: wait for SyncFlush to complete for TLB invalidation timed out Failed to allocate status page %s hws offset: 0x%08x Failed to allocate ringbuffer Failed to map ringbuffer. /build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/intel_ringbuffer.cfailed to quiesce %s whilst cleaning up: %d render ringcan not ioremap virtual address for ring buffer gen6 bsd ringbsd ringblt ringEnabling pipe A in order to enable overlay drm/build/linux-5VIh7j/linux-3.2.78/drivers/gpu/drm/i915/intel_overlay.ccalled with no initialization userspace bug: no overlay buffer used for overlay image can not be tiled overlay underrun, DOVSTA: %x failed to attach phys overlay regs failed to pin overlay register bo failed to move overlay register bo into the GTT <6>[drm] initialized overlay support Overlay, status: 0x%08x, interrupt: 0x%08x Register file at 0x%08lx: OBUF_0Y: 0x%08x OBUF_1Y: 0x%08x OBUF_0U: 0x%08x OBUF_0V: 0x%08x OBUF_1U: 0x%08x OBUF_1V: 0x%08x OSTRIDE: 0x%08x YRGB_VPH: 0x%08x UV_VPH: 0x%08x HORZ_PH: 0x%08x INIT_PHS: 0x%08x DWINPOS: 0x%08x DWINSZ: 0x%08x SWIDTH: 0x%08x SWIDTHSW: 0x%08x SHEIGHT: 0x%08x YRGBSCALE: 0x%08x UVSCALE: 0x%08x OCLRC0: 0x%08x OCLRC1: 0x%08x DCLRKV: 0x%08x DCLRKM: 0x%08x SCLRKVH: 0x%08x SCLRKVL: 0x%08x SCLRKEN: 0x%08x OCONFIG: 0x%08x OCMD: 0x%08x OSTART_0Y: 0x%08x OSTART_1Y: 0x%08x OSTART_0U: 0x%08x OSTART_0V: 0x%08x OSTART_1U: 0x%08x OSTART_1V: 0x%08x OTILEOFF_0Y: 0x%08x OTILEOFF_1Y: 0x%08x OTILEOFF_0U: 0x%08x OTILEOFF_0V: 0x%08x OTILEOFF_1U: 0x%08x OTILEOFF_1V: 0x%08x FASTHSCALE: 0x%08x UVSCALEV: 0x%08x bad pixel format, assuming RGBX888 drmvideonon asle set request?? drmIllum is not supported Pfit is not supported PWM freq is not supported <4>No ACPI video bus found More than 8 outputs detected <3>_ADRgraphic opregion physical addr: 0x%x ACPI OpRegion not supported! IntelGraphicsMemopregion signature mismatch Public ACPI methods supported SWSCI supported ASLE supported Unable to read register 0x%02x from %s:%02x. drm %02X: %02X Unable to write register 0x%02x to %s:%d. ch7xxx not detected; got 0x%02x from %s slave %d. Detected %s chipset, vendor/device ID 0x%02x/0x%02x CH7011CH7009ACH7009BCH7301CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT: %02x drmCH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT: %02x CH7017_VERTICAL_ACTIVE_LINE_OUTPUT: %02x CH7017_ACTIVE_INPUT_LINE_OUTPUT: %02x CH7017_LVDS_PLL_VCO_CONTROL: %02x CH7017_LVDS_PLL_FEEDBACK_DIV: %02x CH7017_LVDS_CONTROL_2: %02x CH7017_OUTPUTS_ENABLE: %02x CH7017_LVDS_POWER_DOWN: %02x Registers before mode setting Registers after mode setting ch7017ch7018ch7019ch701x not detected, got %d: from %s slave %d. %s detected on %s, addr %d Unable to read register 0x%02x from %s:%02x. drmVR00: 0x%04x VR01: 0x%04x VR30: 0x%04x VR40: 0x%04x VR80: 0x%04x VR81: 0x%04x VR82: 0x%04x VR83: 0x%04x VR84: 0x%04x VR85: 0x%04x VR86: 0x%04x VR87: 0x%04x VR88: 0x%04x VR8E: 0x%04x VR8F: 0x%04x Unable to write register 0x%02x to %s:%d. ivch detect failed due to address mismatch (%d vs %d) Unable to read register 0x%02x from %s:%02x. drmTFP410_REV: 0x%02X TFP410_CTL1: 0x%02X TFP410_CTL2: 0x%02X TFP410_CTL3: 0x%02X TFP410_USERCFG: 0x%02X TFP410_DE_DLY: 0x%02X TFP410_DE_CTL: 0x%02X TFP410_DE_TOP: 0x%02X TFP410_DE_CNT: 0x%02X%02X TFP410_DE_LIN: 0x%02X%02X TFP410_H_RES: 0x%02X%02X TFP410_V_RES: 0x%02X%02X Unable to write register 0x%02x to %s:%d. tfp410 not detected got VID %X: from %s Slave %d. tfp410 not detected got DID %X: from %s Slave %d. Unable to read register 0x%02x from %s:%02x. drmSIL164_FREQ_LO: 0x%02x SIL164_FREQ_HI: 0x%02x SIL164_REG8: 0x%02x SIL164_REG9: 0x%02x SIL164_REGC: 0x%02x Unable to write register 0x%02x to %s:%d. sil164 not detected got %d: from %s Slave %d. init sil164 dvo controller successfully! bad type_DSMfailed to evaluate _DSM: %d drmMUX info connectors: %lld Connector id: 0x%016llx port id: %s display mux info: %s aux/dc mux info: %s hpd mux info: %s MUX INFO call failed no _DSM method for intel device failed to get supported _DSM functions VGA switcheroo: detected DSM switching method %s handle ReservedAnalog VGALVDSHDMI/DVI_BHDMI/DVI_CHDMI/DVI_DDisplayPort_ADisplayPort_BDisplayPort_CDisplayPort_DWiDiunknownNo MUX, iGPU onlyNo MUX, dGPU onlyMUXed between iGPU and dGPU//0212//2//////license=GPL and additional rightsdescription=Intel Graphicsauthor=Tungsten Graphics, Inc.parm=i915_enable_ppgtt:Enable PPGTT (default: true)parmtype=i915_enable_ppgtt:intparm=enable_hangcheck:Periodically check GPU activity for detecting hangs. WARNING: Disabling this can cause system wide hangs. (default: true)parmtype=enable_hangcheck:boolparm=reset:Attempt GPU resets (default: true)parmtype=reset:boolparm=vbt_sdvo_panel_type:Override selection of SDVO panel mode in the VBT (default: auto)parmtype=vbt_sdvo_panel_type:intparm=lvds_use_ssc:Use Spread Spectrum Clock with panels [LVDS/eDP] (default: auto from VBT)parmtype=lvds_use_ssc:intparm=lvds_downclock:Use panel (LVDS/eDP) downclocking for power savings (default: false)parmtype=lvds_downclock:intparm=i915_enable_fbc:Enable frame buffer compression for power savings (default: -1 (use per-chip default))parmtype=i915_enable_fbc:intparm=i915_enable_rc6:Enable power-saving render C-state 6. Different stages can be selected via bitmask values (0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. default: -1 (use per-chip default)parmtype=i915_enable_rc6:intparm=semaphores:Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))parmtype=semaphores:intparm=powersave:Enable powersavings, fbc, downclocking, etc. (default: true)parmtype=powersave:intparm=panel_ignore_lid:Override lid status (0=autodetect [default], 1=lid open, -1=lid closed)parmtype=panel_ignore_lid:intparmtype=fbpercrtc:intparm=modeset:Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, 1=on, -1=force vga console preference [default])parmtype=modeset:intparmtype=invert_brightness:intparm=invert_brightness:Invert backlight brightness (-1 force normal, 0 machine defaults, 1 force inversion), please report PCI device ID, subsystem vendor and subsystem device ID to dri-devel@lists.freedesktop.org, if your machine needs it. It will then be included in an upcoming module version.license=GPL and additional rightsalias=pci:v00008086d0000016Asv*sd*bc03sc*i*alias=pci:v00008086d0000015Asv*sd*bc03sc*i*alias=pci:v00008086d00000162sv*sd*bc03sc*i*alias=pci:v00008086d00000152sv*sd*bc03sc*i*alias=pci:v00008086d00000166sv*sd*bc03sc*i*alias=pci:v00008086d00000156sv*sd*bc03sc*i*alias=pci:v00008086d0000010Asv*sd*bc03sc*i*alias=pci:v00008086d00000126sv*sd*bc03sc*i*alias=pci:v00008086d00000116sv*sd*bc03sc*i*alias=pci:v00008086d00000106sv*sd*bc03sc*i*alias=pci:v00008086d00000122sv*sd*bc03sc*i*alias=pci:v00008086d00000112sv*sd*bc03sc*i*alias=pci:v00008086d00000102sv*sd*bc03sc*i*alias=pci:v00008086d00000046sv*sd*bc03sc*i*alias=pci:v00008086d00000042sv*sd*bc03sc*i*alias=pci:v00008086d0000A011sv*sd*bc03sc*i*alias=pci:v00008086d0000A001sv*sd*bc03sc*i*alias=pci:v00008086d00002E92sv*sd*bc03sc*i*alias=pci:v00008086d00002E42sv*sd*bc03sc*i*alias=pci:v00008086d00002E32sv*sd*bc03sc*i*alias=pci:v00008086d00002E22sv*sd*bc03sc*i*alias=pci:v00008086d00002E12sv*sd*bc03sc*i*alias=pci:v00008086d00002E02sv*sd*bc03sc*i*alias=pci:v00008086d00002A42sv*sd*bc03sc*i*alias=pci:v00008086d00002A12sv*sd*bc03sc*i*alias=pci:v00008086d00002A02sv*sd*bc03sc*i*alias=pci:v00008086d000029D2sv*sd*bc03sc*i*alias=pci:v00008086d000029C2sv*sd*bc03sc*i*alias=pci:v00008086d000029B2sv*sd*bc03sc*i*alias=pci:v00008086d000029A2sv*sd*bc03sc*i*alias=pci:v00008086d00002992sv*sd*bc03sc*i*alias=pci:v00008086d00002982sv*sd*bc03sc*i*alias=pci:v00008086d00002972sv*sd*bc03sc*i*alias=pci:v00008086d000027AEsv*sd*bc03sc*i*alias=pci:v00008086d000027A2sv*sd*bc03sc*i*alias=pci:v00008086d00002772sv*sd*bc03sc*i*alias=pci:v00008086d00002592sv*sd*bc03sc*i*alias=pci:v00008086d0000258Asv*sd*bc03sc*i*alias=pci:v00008086d00002582sv*sd*bc03sc*i*alias=pci:v00008086d00002572sv*sd*bc03sc*i*alias=pci:v00008086d0000358Esv*sd*bc03sc*i*alias=pci:v00008086d00003582sv*sd*bc03sc*i*alias=pci:v00008086d00002562sv*sd*bc03sc*i*alias=pci:v00008086d00003577sv*sd*bc03sc*i*depends=drm,drm_kms_helper,i2c-core,video,button,i2c-algo-bitintree=Yvermagic=3.2.0-4-amd64 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_enc_funcsintel_lvds_helper_funcsintel_lvds_connector_helper_funcs__func__.40030find_sectionintel_bios_ssc_frequencyintel_no_opregion_vbt_callback__func__.36943fill_detail_timing_datakzalloc.constprop.3__func__.36939intel_no_opregion_vbt__func__.36953__func__.36857__func__.36865panel_type__func__.36829__func__.36842__func__.36877__func__.36926__func__.36895is_cpu_edpintel_get_adjust_trainCSWTCH.58CSWTCH.60intel_dp_signal_levelsCSWTCH.62intel_clock_recovery_okironlake_get_pp_controlintel_gen7_edp_signal_levels__func__.37838intel_gen6_edp_signal_levels__func__.37825ironlake_edp_backlight_on__func__.37677ironlake_edp_backlight_off__func__.37684intel_dp_link_down__func__.37918intel_dp_destroyintel_dp_adjust_dithering.isra.7intel_dp_mode_validintel_dp_mode_fixup__func__.37517bws.37515intel_channel_eq_ok.isra.9.part.10ironlake_edp_have_panel_power.isra.11ironlake_edp_have_panel_vdd.isra.12ironlake_panel_vdd_off_sync__func__.37640intel_dp_encoder_destroyironlake_panel_vdd_workintel_dp_check_edp__func__.37388intel_dp_aux_ch__func__.37421intel_dp_aux_native_writeintel_dp_set_link_trainintel_dp_aux_native_read_retryintel_dp_get_dpcdintel_dp_start_link_train__func__.37889intel_dp_complete_link_train__func__.37908intel_dp_hot_plug__func__.37938intel_dp_i2c_aux_ch__func__.37476ironlake_edp_pll_on.isra.13__func__.37691ironlake_edp_pll_off.isra.14intel_dp_mode_set__func__.37588intel_dp_sink_dpms__func__.37704ironlake_wait_panel_status.isra.16__func__.37596ironlake_wait_panel_power_cycle__func__.37620ironlake_edp_panel_vdd_on__func__.37631ironlake_edp_panel_on__func__.37661__func__.37612ironlake_edp_panel_off__func__.37668__func__.37616intel_dp_prepareironlake_edp_panel_vdd_off__func__.37652intel_dp_commitintel_dp_dpmsintel_dp_get_modesintel_dp_set_propertyintel_dp_detect__func__.37978kzalloc.constprop.19intel_dp_connector_funcsintel_dp_connector_helper_funcsintel_dp_enc_funcsintel_dp_helper_funcs__func__.38084__func__.37502intel_hdmi_mode_fixupintel_hdmi_dpmsi9xx_write_infoframe__func__.37366__func__.37375intel_hdmi_get_modesintel_hdmi_destroyintel_hdmi_set_propertyintel_hdmi_detectironlake_write_infoframeintel_hdmi_mode_validkzalloc.constprop.9intel_hdmi_mode_setintel_hdmi_enc_funcsintel_hdmi_connector_funcsintel_hdmi_connector_helper_funcsintel_hdmi_helper_funcs__arch_hweight16intel_sdvo_get_dtd_from_modeintel_sdvo_mode_validintel_sdvo_ddc_proxy_funcintel_sdvo_read_byte__func__.37727intel_sdvo_read_response__func__.37777cmd_status_namesintel_sdvo_write_sdvoxintel_sdvo_enc_destroyintel_sdvo_connector_initintel_sdvo_connector_funcsintel_sdvo_connector_helper_funcsintel_sdvo_get_edidintel_sdvo_get_analog_edidintel_sdvo_destroyintel_sdvo_write_cmd__func__.37739sdvo_cmd_names__func__.37768intel_sdvo_ddc_proxy_xferintel_sdvo_enable_hotplugintel_sdvo_get_valueintel_sdvo_set_valueintel_sdvo_set_timingintel_sdvo_set_target_inputintel_sdvo_dpms__func__.37987intel_sdvo_get_modessdvo_tv_modes__func__.38036intel_sdvo_set_propertyintel_sdvo_set_output_timings_from_modeintel_sdvo_set_input_timings_for_mode.part.9intel_sdvo_mode_fixupintel_sdvo_create_enhance_property__func__.38277__func__.38258__func__.38268intel_sdvo_mode_set__func__.37906CSWTCH.72kzalloc.constprop.14intel_sdvo_lvds_initintel_sdvo_tv_inittv_format_namesintel_sdvo_dvi_initintel_sdvo_analog_initintel_sdvo_detect__func__.38049intel_sdvo_ddc_proxyintel_sdvo_enc_funcs__func__.38303intel_sdvo_helper_funcs__func__.37997__func__.38215force_audio_namesbroadcast_rgb_namesintel_panel_get_brightnessis_backlight_combination_mode__print_once.37397__func__.37398intel_panel_compute_brightnessi915_panel_invert_brightnessintel_panel_actually_set_backlight__func__.37436__func__.37423intel_panel_update_statusintel_panel_bl_ops__func__.37477__mod_invert_brightnesstype199__param_invert_brightness__param_str_invert_brightness__mod_invert_brightness198get_reservedget_clockget_dataset_clockset_datagmbus_funcintel_i2c_quirk_set.part.1intel_i2c_quirk_xfergmbus_xfer__key.37385names.37381gmbus_algorithmmap_pin_to_reg.37279kzalloc.constprop.1intel_fb_find_or_create_single__func__.38283intelfb_opsintel_fb_helper_funcs__func__.38328__mod_license267intel_tv_dpmsintel_tv_destroyintel_tv_set_propertytv_modesintel_tv_mode_find.isra.2intel_tv_mode_validintel_tv_mode_fixupintel_tv_get_modesinput_res_tableintel_tv_mode_setsdtv_csc_yprpbhdtv_csc_yprpbcomponent_levelsintel_tv_detect_type.isra.3__func__.37602intel_tv_detectreported_modesintel_tv_connector_funcsintel_tv_enc_funcsintel_tv_helper_funcsintel_tv_connector_helper_funcs__func__.37701ntsc_m_levels_compositentsc_m_levels_svideontsc_m_csc_compositentsc_m_csc_svideofilter_tablentsc_j_levels_compositentsc_j_levels_svideontsc_j_csc_compositentsc_j_csc_svideopal_m_levels_compositepal_m_levels_svideopal_m_csc_compositepal_m_csc_svideopal_n_levels_compositepal_n_levels_svideopal_n_csc_compositepal_n_csc_svideopal_levels_compositepal_levels_svideopal_csc_compositepal_csc_svideointel_dvo_mode_validintel_dvo_mode_fixupintel_dvo_detectintel_dvo_mode_setintel_dvo_dpmsintel_dvo_get_modesintel_dvo_destroyintel_dvo_enc_destroykzalloc.constprop.2intel_dvo_enc_funcsintel_dvo_devicesintel_dvo_connector_funcsintel_dvo_connector_helper_funcsintel_dvo_helper_funcsring_spacepc_render_get_seqnoring_get_seqnoring_write_tailironlake_disable_irqironlake_enable_irqgen6_ring_put_irqblt_ring_put_irqgen6_bsd_ring_put_irqgen6_render_ring_put_irqgen6_ring_get_irqblt_ring_get_irqgen6_bsd_ring_get_irqgen6_render_ring_get_irqrender_ring_cleanupcleanup_status_pagegen6_bsd_ring_write_tail__func__.37592init_ring_common__func__.37271init_render_ring__func__.37291trace_i915_ring_wait_endi915_disable_irqbsd_ring_put_irqrender_ring_put_irqi915_enable_irqbsd_ring_get_irqrender_ring_get_irqgen6_ring_get_seqnoCSWTCH.25__func__.37425__key.37497__func__.37487__func__.37499__func__.37509gen6_ring_dispatch_execbuffergen6_add_requestblt_ring_flushring_dispatch_execbufferring_add_requestbsd_ring_flushgen6_ring_flushpc_render_add_requestrender_ring_dispatch_execbufferrender_ring_add_requestrender_ring_flushgen6_render_ring_flushintel_ring_sync__func__.37645uv_hsubsamplinguv_vsubsamplingcalc_swidthswupdate_polyphase_filtery_static_hcoeffsuv_static_hcoeffsintel_overlay_release_old_vid_taili830_activate_pipe_a__func__.37320intel_overlay_map_regscheck_gamma_boundsintel_overlay_off_tailintel_overlay_recover_from_interruptintel_overlay_do_wait_requestintel_overlay_release_old_vid__func__.37553__func__.37346__func__.37595__func__.37608.LC2ivb_get_colorkeysnb_get_colorkeyintel_enable_primaryintel_destroy_planeivb_update_colorkeyivb_disable_planesnb_update_colorkeysnb_disable_planeintel_update_planesnb_update_plane__func__.37314ivb_update_plane__func__.37252snb_plane_formatsintel_plane_funcsasle_set_backlightintel_opregion_video_eventsystem_opregion__func__.39692__func__.39700CSWTCH.18intel_opregion_notifier__func__.39794ch7xxx_mode_validch7xxx_readb__func__.37293ch7xxx_dump_regsch7xxx_writeb__func__.37303ch7xxx_detectch7xxx_mode_setch7xxx_destroych7xxx_initch7xxx_ids__func__.37313ch7xxx_dpmsch7017_detectch7017_mode_validch7017_readch7017_dump_regs__func__.37333ch7017_writech7017_destroych7017_dpmsch7017_mode_set__func__.37323ch7017_init__func__.37301ivch_detectivch_mode_validivch_read__func__.37284ivch_dump_regsivch_write__func__.37294ivch_mode_setivch_destroyivch_init__func__.37302ivch_dpmstfp410_mode_validtfp410_mode_settfp410_readb__func__.37280tfp410_dump_regstfp410_detecttfp410_getidtfp410_dpmstfp410_destroytfp410_initsil164_mode_validsil164_mode_setsil164_readbsil164_dump_regssil164_detectsil164_dpmssil164_destroysil164_init__func__.37298compat_i915_cmdbuffercompat_i915_alloccompat_i915_getparamcompat_i915_irq_emitcompat_i915_batchbufferintel_dsm_platform_mux_infointel_dsm_privintel_dsm_guid__func__.36477CSWTCH.2CSWTCH.4intel_dsm.constprop.1__func__.36436intel_dsm_detect__func__.36493__func__.36505__mod_alias412__mod_alias411__mod_alias410__mod_alias409__mod_alias408__mod_alias407__mod_alias406__mod_alias405__mod_alias404__mod_alias403__mod_alias402__mod_alias401__mod_alias400__mod_alias399__mod_alias398__mod_alias397__mod_alias396__mod_alias395__mod_alias394__mod_alias393__mod_alias392__mod_alias391__mod_alias390__mod_alias389__mod_alias388__mod_alias387__mod_alias386__mod_alias385__mod_alias384__mod_alias383__mod_alias382__mod_alias381__mod_alias380__mod_alias379__mod_alias378__mod_alias377__mod_alias376__mod_alias375__mod_alias374__mod_alias373__mod_alias372__mod_alias371__mod_alias370__mod_alias369__module_depends____versions__mod_intree17__mod_vermagic5unregister_framebufferns_to_timevaldrm_framebuffer_cleanupi915_gem_faultintel_ring_beginstrcpypci_save_statedrm_kms_helper_poll_finiintel_teardown_gmbusdrm_openintel_panel_get_max_backlightdrm_mm_scan_remove_blockdrm_fasyncdrm_mode_vrefreshintel_agp_enabledvm_insert_pfndrm_fb_helper_single_add_all_connectorsioread32intel_get_load_detect_pipedrm_fb_helper_initdma_opsi915_gem_execbufferdrm_polldrm_fb_helper_debug_enterdrm_mm_get_block_range_genericqueue_delayed_workintel_finish_page_flip_planedrm_mode_object_finddrm_vblank_puti915_driver_unloadintel_fbdev_set_suspenddrm_kms_helper_poll_disabledrm_mode_crtc_set_gamma_sizedev_get_drvdataintel_wait_for_pipe_offi915_read_mch_valintel_dpd_is_edpi915_gem_leavevt_ioctldrm_mode_legacy_fb_formati915_gem_detect_bit_6_swizzledrm_fb_helper_fill_fixbacklight_device_unregisteri915_gem_object_save_bit_17_swizzle_copy_from_userintel_disable_fbcintel_crtc_mode_getpci_enable_deviceintel_pch_panel_fittingi915_gfx_valon_each_cpui915_gem_entervt_ioctliowrite32pcibios_align_resourcedrm_kms_helper_poll_initintel_encoder_destroydrm_ut_debug_printkdrm_mm_get_block_genericintel_connector_attach_encoderi915_read8drm_framebuffer_initironlake_init_pch_refclkintel_panel_setup_backlightdrm_property_createdrm_mm_search_free_in_rangeintel_sprite_set_colorkeydrm_pci_initintel_prepare_page_flipintel_modeset_gem_initpci_iomapdrm_fb_helper_setcmap__this_moduletrace_seq_printfdrm_helper_disable_unused_functionspci_enable_msi_blocksnprintfdrm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